According to the specification of a previously developed ATA (Advanced Technology Attachment) interface, the command set only supports the access to a non-extractable storage device while the access to an extractable storage device is not imparted. Due to the development of removable storage device and practical needs, an Advanced Technology Attachment Packet Interface (hereinafter “ATAPI”) is developed with a specification of Advanced Technology Attachment with Packet Interface Extension (hereinafter “ATA/ATAPI”). The ATA/ATAPI whose command set permits access to extractable storage devices has become the mot common interface specification nowadays for the communication of magnetic disc drives, hard disc drives and optical disc drives with a computer system.
Furthermore, the ATA/ATAPI incorporates therein a Serial ATA (SATA) specification. A conventional Parallel ATA (PATA) specification, after making a brilliant history, has been found several serous design problems for current chip designers. These problems include requirements of 5 volts signals, a large number of pins and complicated bus means. The SATA interface is then developed to solve the above-mentioned problems. The SATA interface allows the number of storage interfaces to grow with the development of PC platforms and is compactable with current operating systems and drivers. In addition, it can work with lowered voltage, reduced pin number and simplified bus means. Moreover, the SATA interface provides enhanced transfer rate. It is expected that next generation of SATA specification will have a higher transfer rate, which may be up to double.
Nevertheless, as SATA interface is a newly stipulated specification and there are still peripherals operated with PATA interfaces, a bridge chip for coordinating the SATA interface and the PATA interface is developed. FIG. 1 illustrates a typical disposition of a bridge chip between a SATA-interfaced host and a PATA-interfaced device. In response to a software command, the SATA-interfaced host 10 undergoes data transmission to/from the bridge chip 11 according to the SATA specification. On the other hand, the bridge chip 11 is capable of transmitting data to/from the PATA-interfaced device 12 according to the PATA specification. In this way, it is possible to communicate the SATA-interfaced host 10 with the PATA-interfaced device 12 via the bridge chip 11.
In the ATA/ATAPI specification, transmission in a Programmed I/O mode (PIO mode) and transmission in a Direct Memory Access mode (DMA mode) are recited. In the PIO mode, the ATA/ATAPI-interfaced device accesses to a memory and perform associated operations under the essential control of the CPU. In the DMA mode, on the other hand, similar operations can be performed by the ATA/ATAPI-interfaced host controller and the drivers without the management of the CPU. Consequently, unlike the PIO mode, transmission in the DMA mode need not interrupt the CPU for data transmission. However, not all ATA/ATAPI-interfaced devices support the DMA mode. For example, referring to FIG. 1, when the computer system executes certain software so as to issue a read/write command but the PATA-interfaced device 12 does not support the DMA mode, the PATA-interfaced device 12 will terminate the execution of the read/write command while sending an error message to the SATA-interfaced host 10 in response. Accordingly, the SATA-interfaced host 10 resends a substitutive read/write command for the slower PIO mode data transmission. Such a process will remarkably reduce the performance of the entire system.